Computer Science 251
Computer Organization

Dickinson College
Fall Semester 1999
Grant Braught

Sample Project Assignment:

Even Parity Checker: (Due: 2/2/22)

For this project you will design and test a four bit odd number detector. Your circuit should output a 1 if the 4 bit input represents an odd number and output a 0 if the 4 bit input represents and even number.

For example:

Input: Output: 0101 1 -- The input is an odd number (5) 0010 0 -- The input is an even number (2)

Sample Design Document:

NOTE: Your design document should be divided into 5 sections: Introduction, Design, Test Cases, Implementation and Test Results. I strongly suggest that you make a first pass at the Introduction, Design and Test Cases sections before beginning any implementation. This will ensure that you have a solid understanding of what you are trying to do before you begin. Inevitably you will need to go back and revise these once you begin implementation, and that is acceptable.

Note also that the Introduction, Design and Test Cases sections of the design docuement will be graded independently of your implementation. Thus, if you do a quality design you will score quite well on these sections even if you have difficulites with your implementation. Therefore, I again strongly suggest that you complete these sections before beginning any implementation. Then modify them as needed during implementation.

Introduction:
NOTE: The introduction should state your understanding of what is to be done in this project. This statement can be similar to what was given to you in the project assignment but should be written in your own words. I suggest reading and understanding the project assignment. Then sit down and write your introduction without looking back at the project assignment. While this may seem redundant, it is very good practice for when you are the one defining the project!

In this project we design implement and test an even number detector. This circuit is capable of determining if a 4 bit binary input is odd or even. The circuit accepts as input a 4 bit binary number and generates one bit as the output. The output bit will be 1 if the input is even and 0 if the input is odd. Figure 1 shows a black box representation of the circuit:

Figure 1: Black-box Even Number Detector.

Design:

NOTE: The design section should describe your design. You should discuss the methods and tools that you used to develop your design. Use diagrams, equations and tables when they most clearly present an idea. You should discuss the design decisions you made. This includes mentioning alternative designs that are not immediately inferior and discussing why the design you chose is better. This is also the place to state and justify any assumptions that you have made.
 To design our even number detector we expressed the function in truth table shown in Table 1. From this table a sum-of-products expression for the even number detector was generated (eq. 1). _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Z = A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D (1) A SOP expression can always be implemented in a straight forward manner. However, in this case there is a much more efficient solution. Looking at the truth table we noted that Z=1 only when D=0. Thus, it appears that the even number detector can be implemented using a single not gate. To verify this observation we applied the rules of Boolean Algebra to simplify equation 1 as follows: _ _ _ _ _ _ _ _ _ _ _ _ Z = A B D (C + C) + A B D (C + C) + A B D (C + C) + A B D (C + C) Distributive + _ _ _ _ _ _ _ _ = A B D + A B D + A B D + A B D Inverse + _ _ _ _ _ = A D (B + B) + A D (B + B) Distributive + _ _ _ = A D + A D Inverse + _ _ = D (A + A) Distributive + _ = D Inverse + Thus, the function of determining if a number is even requires no more than inverting the least significant bit. Table 1: Truth Table for Odd Number Detector

Test Cases:
NOTE: Here you should discuss how you intend to test your implementation. This should include your justification for using exhaustive or sampled testing. If you use sampled testing you must justify the test cases that you chose and argue that they are sufficient to warrant a high degree of confidence in the implementation. A brief statement about how you will verify the correctness of the tests also belongs in this section.

Because the number of inputs is small, the even number detector can be tested exhaustively. This will be done by VHDL test bench that drives the inputs with all 16 possible inputs (see table 1). The output generated in response to each input pattern will then be compared by hand to the Z value in table 1 to check for correctness.

Implementation:

NOTE: This section should contain a quick tour of your implementation code. It should document dependencies on any other code. Do not cover the code line by line. If the reader desires that level of detail they should be able to read your code. It is the job of this section to help them find the correct code to read! To help those that need to read you code it should be commented liberally. If your implementation contains some particularly unique or special feature you should document that here.

If you are unable to get a working implementation this section is where you should document your effort. Clearly state which parts of your implementation are working and which parts are not working. Describe where you are stuck and propose directions of work that will help you become unstuck.

The file evendet.v attached to this document contains the VHDL implementation of the even number detector. The evendet entity makes use of the notGate component defined in the lgates.v file to invert the LSB of the input. The file even_test.v attached to this document contains the VHDL test-bench for the even number detector. This test-bench implements the exhaustive tests described above.

Test Results:

NOTE: This section should clearly, concisely and honestly present the results of your tests. Do not just dump data. All data that is presented should be discussed. Information should be presented in tables and graphs when possible. The raw tables output by the Vanilla VHDL tools are rarely appropriate for inclusion here, although edited and documented versions may be useful. If at the time of submission there are any tests that are still failed, they must be documented and a corrective action should be proposed. Undocumented failed tests, incomplete testing and falsification of test results will be treated significantly more severely than honest documentation of failed tests. The time available for these projects is limited and it not unreasonable to have some remaining bugs, but they must be documented!

The lgates.v, evendet.v and even_test.v files were all analyzed into a VHDL library using the va87 Vanilla VHDL analyzer. The vs87 simulator was then used to simulate the system while tracing the tst and e signals from the even_test.v test-bench. The output of the test bench has been displayed graphically in figure 2 through the use of the vanplot and gnuplot software packages.

Figure 2: Even Number Detector Test Bench Output

In figure 2, e represents the output of the even number detector and tst(3)...tst(0) are the inputs. By comparing the inputs to the output it can be seen that e is high (true, 1) only when an even number of the tst inputs are high. Thus, because the tst presented every possible input to the circuit and e is correct in all cases, the circuit is correct.