CS251 - Computer Organization

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Computer Science 251
Computer Organization

Dickinson College
Fall Semester 1999
Grant Braught

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Class #30 - Design Issues
Design Issues:
       Often choices will have to be made on how some aspect of the computer will behave.
       Sometimes technical issues will dictate the behavior of the hardware:
            Latches are edge triggered instead of level triggered because it is difficult to produce very narrow clock pulses.
            SRAM & DRAM use a 2 level address decoding scheme.
       More often the behavior of the hardware will be flexible and can be adjusted based on how we will use it:
            The ALU was designed to support subtraction.
            Will memory be byte addressable or word addressable?
            The final structure of the data path will depend on the instructions our machine supports.

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Byte Addressable -vs- Word Addressable
       We'll use this as an example of how these decisions can be made.

Think of memory as a stack of bytes (a DRAM):
       This image shows the different options we have in accessing memory:

       Word Addressable:
            Memory Address 0: Bytes 0-3 = "BOAT"
            Memory Address 1: Bytes 4-7 = "DOCK"
       Byte Addressable:
            Memory Address 0: Bytes 0-3 = "BOAT"
            Memory Address 1: Bytes 1-4 = "OATD"
            Memory Address 2: Bytes 2-5 = "ATDO"
            etc...

The issue:
Which bytes of memory do we get when we read a memory address?
This will ultimately depend on several factors:
       How we want to use our computer,
       The capabilities of our existing hardware,
       Our design philosophy (RISC -vs- CISC).

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Let's see why this becomes an issue:
       The memory situation above could be created from the C++ code: char word1[4] = "BOAT"; char word2[4] = "DOCK";             C++ also offers a byte class that will allow integers in the range -128...127 to be stored in a single byte.
            This saves memory when you know the values you are storing are small. (an int is 4 bytes!)
            Java has similar types.

       Some common operations might be: register char x, y; x = word1[0]; // x = B y = word2[2]; // y = C The question is how do we implement these operations on our computer?
Humm...

x = word1[0];
       Load memory address 0 (bytes 0-3) into a register, say R0.
       Perform the operation R0 = R0 & 0x000000FF R0 = T A 0 B & 0x000000FF = 0x00 0x00 0x00 0xFF ---------------------------------- R0 = 84 65 79 66 (ASCII Values) & 0x000000FF = 0x00 0x00 0x00 0xFF ---------------------------------- R0 = 01010100 01000001 01001111 01000010 & 0x000000FF = 00000000 00000000 00000000 11111111 --------------------------------------------------- R0 = 00000000 00000000 00000000 01000010 = B y = word2[2];
       This depends on if we have a byte addressable or word addressable memory!

       For a Byte Addressable Computer:
            Load memory address 6 (bytes 6-9) into a register, say R0.
            Perform the operation R0 = R0 & 0x000000FF R0 = ? ? K C & 0x000000FF = 0x00 0x00 0x00 0xFF ---------------------------------- R0 = 0x00 0x00 0x00 C        For a word addressable computer:
            Load memory address 1 (bytes 4-7) into a register, say R0.
            Perform the operation R0 = R0 & 0x00FF0000 R0 = K C 0 D & 0x00FF0000 = 0x00 0xFF 0x00 0x00 ---------------------------------- R0 = 0x00 C 0x00 0x00             Shift R0 16 bits to the right shifting in 0's on the left. R0 = 0x00 0x00 0x00 C

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Now that we understand the problem and the issues...
What factors will affect our decision?
Several things:
       Ultimately the goal is speed.
            With the constraint that the hardware doesn't become unmanagable.
       We are building a RISC machine so we want to keep the instruction set small and simple.
            One instruction for moving data from memory to registers would be ideal.

Which type of addressing should our computer use?
I'd argue that byte addressing is the way to go.
       It provides the fastest access to individual bytes on our machine.
            With word addressing we may require up to 24 shift operations to get to a byte!
       So in hardware our computer will support byte addressing but will still load a word at a time.
            To load a byte we'll load the word with that byte in the low 8 bits,
            and then do an and with 0x000000FF.

What other options are available?
Several:
       The MIPS architecture (RISC) is similar to ours but also provides a Barrel Shifter:
            The Barrel Shifter can shift any specified number of bits in one operation.
            Thus, it only takes one operation to move a byte to the LSB position.
            This might argue for Word Addressable but MIPS is still byte addressable.
       The INTEL architecture (CISC) provides additional byte oriented instructions:
            It has special hardware in the bus control unit.
            This hardware selects specific bytes from a word,
            and shifts them to the LSB position automatically.
            In byte I/O instructions the 2 LSbits of the address are used to pick a byte from the word.
            That byte is then transferred on the low 8 bits of the bus.
            INTEL also provides half word (16 bit) I/O Instructions.

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What about writing a byte back to memory?
Several steps:
       Fetch the word that starts with the byte to be written into a register.
       AND that register with 0xFFFFFF00
       OR that result with the register containing the byte to be written. word2[1] = U; R0 = ? K C 0 & 0xFF 0xFF 0xFF 0x00 ---------------------------- ? K C 0x00 | 0x00 0x00 0x00 U ____________________________ ? K C U
       Store the resulting word back to memory.

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