CS251 - Computer Organization
Computer Science 251
Fall Semester 1999
Class #22 - Flip-Flops and Register Banks
The Clocked D Latch:
When Clock = 1: The Q output follows the D input.
The !Q output is the logical inversion of Q.
When Clock = 0: The Q output remains constant.
This is caused because the S & R inputs are both 0.
What is the output of a D latch if the following signals appear on D and Clock?
How does this differ from the abstract one bit memory that we described earlier?
In this memory the output can change any time the clock is high.
In the abstract one bit memory we described last class the output could only change on a leading edge.
Let's see how we can achieve that ideal using this circuit.
Why do we care if the output changes on a leading edge or if it changes when the clock is high?
This is a technical issue.
If the output can change any time the clock is high, the desired output
must be held on the input for the entire time the clock is high. If the input happens
to change even an instant before the clock we'll get the wrong output. This turns out
to be a significant challenge technically. However, by only allowing the output to change
on a leading edge of the clock, the input need only be held constant during the instant of
the leading edge. Which is a much easier thing to do.
First, We can bundle all of the details of a Clocked D Latch in to a block:
We'll use this block in schematics to represent a Clocked D Latch.
This block behaves exactly like the circuit above.
How would the Clocked D latch behave if we invert the clock input?
The Q output will follow D when the clock is low.
Inverting the clock makes the circuit's clock high when the input clock is low.
Using the same inputs as above the Q output is now:
The D Flip-Flop:
A D Flip-Flop is constructed from two Clocked D Latches.
This configuration is commonly known as a master and slave configuration.
While, probably not politically correct this is the terminology used to refer to this type of circuit.
How would this circuit respond to the following D and Clock inputs?
For now we'll consider the Qm and Ds signals explicitly.
The Qm = Ds signal follows the D input when the clock is low.
The output of the Master Latch changes when the clock is low.
The Q output follows the Qm = Ds output when the clock is high.
The output of the Slave Latch changes when the clock is high.
The net effect of this is that the output of the Slave becomes the input of the Master on a leading edge.
We'll bundle all of the details of a D Flip Flop into a block also:
Note: The NOT gate on the clock of the Master Latch is included in the D Flip-Flop block!
The behavior of the D flip-flop is most simply expressed as:
Q becomes D on a leading edge of the clock.
Building a Register (a 32 bit latch):
Recall that we can line up 32 of these D-Flip-Flops next to each other to produce a 32 bit latch.
Each of the 1 bit memories is a D Flip-Flop.
Note: Even though the 32 bit Latch contains Flip-Flops and not latches, it is still commonly called a Latch.
Don't ask me why, it just is.
Using the Registers:
Recall that the K&S Model 1 has a register bank:
It had 4 registers (R0, R1, R2, R3) and 3 dials.
One dial selected the register to be written to.
The other two dials selected the A and B outputs.
Now that we know how to build the registers our next task is to build the Register Bank.
We can start by lining up 4 of the 1 Word (32 bit) Latches.
The same 32 bits are presented to every register.
This is the C Bus in the K&S Model 1.
A 1 is placed on the select line for the desired register.
Done in the K&S by turning the Knob in the Register Bank.
When a leading edge appears on the Clock the data will be written to the selected register.
All of the registers present their contents on their respective outputs.
We'll resolve the issue of selecting the proper output shortly.
But first we need to automate the selection of the register for writing.
The Select (S) lines pick one of the Data (D) lines to set to a 1.
The line selected is determined by interpreting the Select lines as a binary number.
Thus, in a 3 to 8 decoder: S2,S1,S0 = 011 will set D3 = 1
The remaining lines are set to 0's.
Thus, using a Decoder we can automatically set the correct Select line for writing our registers.
By automatically, I mean using bits just as we did in the K&S Model 1 with microprogramming.
So, the register to be written could be selected using 2 bits.
Next time... the read circuits for the register bank.