CS251 - Computer Organization
Computer Science 251
Computer Organization
Dickinson College
Fall Semester 1999
Grant Braught

Class #21 - 1 Bit Memories and Latches

The K&S Model 1: ( simulation )
       We have built the ALU
       What remains is to build the Registers and the Memory
            We'll attack the registers next.
            Then we'll look at some types of commercial memory.
       Then add a control unit and we'll have a working computer...


What is a register?
It is a memory cell.
       It is capable of storing some number of bits.
       In its simplest form that means storing a single bit.

If we have a memory cell that can store 1 bit can we make one that can store 32 bits?
Sure, just line up 32 of the 1 bit memory cells next to each other.
       Just like with the ALU's.
       So what we need to build our registers is a 1 bit memory cell...

Abstractly we can look at this as:        When there is a signal on the write line
       The value at the input is copied into the memory cell
            The input can change from 1 to 0 as much as it wants,
            but the stored value only changes when there is a signal on the write line
       The value stored in the memory cell always appears at the output.

In more detail:


       A transition from low to high on the write line copies the input into the latch.
            This transition from low to high is called a leading edge.
       A transition from high to low will be called a trailing edge.
       The output always reflects the contents of the latch regardless of the input or write lines.

How does this differ from the circuits we have been working with?
In the circuits we have used so far the output is determined directly by the inputs.
       If the input changes the output will change (after some propagation delay.)
       If the inputs remain constant then the output will remain constant.
            These circuits are called combinational logic circuits.
       Here the output is affected by past inputs to the circuit.
            Circuits of this type are called sequential logic circuits.

To make a latch that can store more than one bit just line up several of these one bit latches.        Every 1 bit latch receives the same write signal.
            Thus, all of the input bits will be stored simultaneously.

Wide latches will often appear in schematics using a simpler diagram:        Both the input and output lines here contain 32 bits.
       Each input and output is routed to the appropriate one bit latch.


A Simple Sequential Circuit:
       Before building a latch let's look at a sequential logic circuit with only one gate: Why is this a sequential circuit and not a combinational circuit?
The output is not uniquely determined by the input.
       Because the output is fed back into the input...
       the current output has an effect on the next output.

What is the output of this circuit if J=1 (Assume Q=0 to start.)
The output is 0. 1 NOR Q = 1 NOR 0 ---> Q = 0 1 NOR Q = 1 NOR 0 ---> Q = 0 What is he output of this circuit if J=0 (Assume Q=0 to start.)
The output oscillates. 0 NOR Q = 0 NOR 0 ---> Q = 1 0 NOR Q = 0 NOR 1 ---> Q = 0 0 NOR Q = 0 NOR 0 ---> Q = 1 0 NOR Q = 0 NOR 1 ---> Q = 0 etc... Can this be used as a memory element?
Not really because it doesn't remember its input and the output can be unstable.


The D Latch:
       The following is a more complicated sequential circuit known as a D Latch:
What is Q when D = 0 (Assume Q = 0 and !Q = 0 to start.)?
Q = 0 _ D NOR Q = 0 NOR 0 ---> Q = 1 _ _ D NOR Q = 1 NOR 1 ---> Q = 0
Does it matter what Q and !Q are to start?
No, assume Q = 1 and !Q = 0 to start. _ D NOR Q = 0 NOR 1 ---> Q = 0 _ _ D NOR Q = 1 NOR 0 ---> Q = 0 _ D NOR Q = 0 NOR 0 ---> Q = 1 _ _ D NOR Q = 1 NOR 0 ---> Q = 0
What happens to Q if D changes to 1?
Q changes to 1. (Assuming Q = 0 and !Q = 1 from above.) _ D NOR Q = 1 NOR 0 ---> Q = 0 _ _ D NOR Q = 0 NOR 0 ---> Q = 1 _ D NOR Q = 1 NOR 1 ---> Q = 0 _ _ D NOR Q = 0 NOR 0 ---> Q = 0
So in a D Latch, Q = D and !Q = !D

Is this a memory?
Not even close... it is just the inputs!
       This may seem useless, why not just use D and !D and avoid all the extra gates?!?
       Well, if we could get Q to hold the previous value of D when D changes we get a memory!
       To do that we'll build on this circuit...


A Clocked D Latch:        To control when the output is allowed to change we can insert a clock signal

If the clock is a 1 what are S and R?
When the clock is a 1, S=D and R=!D.
       So with the clock = 1 this circuit behaves exactly like a D Latch.
            When Clock = 1, Q = D and !Q = !D

When the clock is a 0 what are S and R?
When the clock is a 0, S=0 and R=0.
       When one input to an AND is 0 the output is 0.

What happens to Q and !Q when S and R are both 0?
Q and !Q remain unchanged - they remember their last state. clock = 0, S=0, R=0 _ S NOR Q = 0 NOR Q = Q _ _ R NOR Q = 0 NOR Q = Q        Thus, when the clock is 1 the output Q reflects the value of D
       and when the clock is 0 the output Q will retain the value of D from the last time the clock was 1.

Is this a memory?
Yes! The value of Q remembers what D was the last time the clock was a 1.
Is this exactly the type of memory we talked about earlier?
No, the signal for our 1 bit latch was a rising edge. The signal here is just a 1.
       Thus, if D changes while the clock is 1 the output also changes.
       So we don't quite have the full 1 bit latch yet.
            Next class...