What makes a good circuit?
Low cost
Fewer gates
Fewer inputs per gate
High speed
Fewer levels of logic
Correct operation
Gate Propagation Delays
Each logic gate takes some amount of time to calculate its output from its input.
So if an input to a gate changes the output will not change until some amount of time has passed.
This amount of time is called the Gate Propagation Delay.
The Gate Propagation delay varies from gate to gate.
It will also differ between different versions of the same gate.
Generally, faster gates cost more money!
Typical Gate Propagation Delays:
We will be using the following Gate Propagation Delays for our hand calculations:
When gates are combined into circuits the circuit will have a propagation delay.
The propagation delay of the circuit is the worst case time required for the output(s) to become correct after a change in the input(s).
So asking about the propagation delay is essentially asking how long it is necessary to wait after a change has occurred to be sure the answer is correct.
Propagation Delays and Computer Speed:
Propagation delays are essentially what determines the speed of today's computers. If we assume that a computer executes 1 machine language instruction per clock tick, then the delay of the longest machine language instruction determines how fast the clock can tick. Or said another way, the propagation delay of the circuit that executes the machine language instructions determines how long the computer must wait to be sure the result of an instruction is correct.
What is the propagation delay of the following circuit?
To answer this we must consider all possible changes that can occur and find the worst case. Then if we always wait that long we will be sure to have the correct answer regardless of what has happened.
The First Row:
The Second Row:
The Third Row:
So, while the final output is the same as it was at the start it flipped values during the computation. Thus, the answer was not known to be correct until 7.5 ns + 6.5 ns = 14.0 ns.
This can also be seen using a VHDL simulation and testbench:
propDelay.v
propDelay_test.v
Timing Diagram of the circuit for these test patterns:
Propagation Delays:
At 50 ns the inputs become 01 but the output does not change immediately.
This is the scenario described above for the First row of the table.
At 250 ns the inputs become 11...
Initially the output is correct but...
It changes a short time later to an incorrect value...
Then becomes correct again after another short time.
This is the scenario described above for the third row.
Difficult to tell how long these delays are from the plot.
Look at the vtab output from VHDL:
Here we see the input go from 00 to 01 between 50 & 51 ns
The output goes from 0 to 1 between 56 & 57 ns.
Delay of between 6 and 7 ns. Agrees with estimate of 6.5 ns from above.
The input goes from 00 to 11 between 250 and 251 ns.
The output goes to 1 between 256 and 257 ns...
and back to 0 between 263 and 264 ns.
Delay of between 13 and 14 ns. Estimate of 14 ns is at high end.
Gate delays used for hand estimates are simplified
The actual gate delay's depend on the direction of the change in inputs and outputs (0 to 1) or (1 to 0).
To keep hand calculations manageable, we use the longest delay for each gate.
Hand estimate should always be greater than or equal to observed delay.
The remainder of the possible scenarios are as follows:
So if we wait 14.0 ns after any change before looking at the answer
Then, we know for sure that no matter what the change was the answer will be correct.
Estimating Propagation Delays:
What is the propagation delay for the following circuit?
Looking at all combinations is not the best way to do this.
That is kind of tedious...
Besides we are only really concerned with the worst case...
The following process acheives the same result.
In the worst case the OR gate will require 7.0 ns to compute D.
The NOT bubble at the input to the AND gate requires 4.5 ns in the worst case.
Thus, in the worst case the inputs to the AND gate arrive at 4.5 ns.
The AND gate requires 7.5 ns to compute its output making C available after 12.0 ns (4.5 + 7.5)... in the worst case!
Thus, the inputs to the NOR gate arrive at MAX(7.0, 12.0) = 12.0 ns.
The MAX operation accounts for the worst case!
In the worst cast, the NOR gate requires an additional 5.0 ns to compute Z.
Thus, the total propagation delay is 17.0 ns (12.0 + 5.0).
The following diagram illustrates this timing:
Motivation for Logic Simplification:
Consider a 3 bit Odd Number Detector
The odd number detector will output a 1 if its 3 bit input is an odd number in unsigned binary representation. Otherwise, the odd number detector will output a 0.
How would you build a circuit to compute this function?
Using the methods from the last class:
Express the function as a truth table.
Express the truth table as an SOP expression.
Create a circuit from the SOP expression.
What does the truth table for a 3 bit Odd Number Detector Look Like?
As follows:
What is the straight forward SOP expression that we can generate from this truth table?
As follows:
What does the circuit implementation of this expression look like?
As follows:
How long will it take to compute E using this circuit?
4.5ns + 7.5ns + 7.0ns = 19.0ns.
4.5ns for the NOT gates.
7.5ns for the AND gates.
7.0ns for the OR gate.
Is there an easier way to express E?
Yes, E = C
What does this circuit look like?
It is trivial... Just a wire!
Which way would you want to build the circuit?
The second way, I hope!
Why?
It uses less gates!
Using less gates has several possible advantages:
Cheaper - Less gates cost less money.
Smaller - Uses less space on a chip.
More reliable - Less gates means less opportunities for failure.
Faster??? Maybe but not always.
This gives us several ways to evaluate our circuits:
Size/Cost: Measured by number of gates.
Speed: Time measured using the gate propagation delays.
Using a SOP expression does not necessarily give us the best implementation.
Sometimes you can have a flash of inspiration and see a simpler expression...
Sometimes you can't!
This is where logic simplification with Boolean Algebra comes in... Next class...